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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
128K x 36 and 256K x 18 Bit Flow-Through ZBTTM RAM Synchronous Fast Static RAM
The ZBT RAM is a 4M-bit synchronous fast static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back-to-back read/write and write/read cycles. The MCM63Z737 is organized as 128K words of 36 bits each and the MCM63Z819 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, a 2-bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQ), and all control signals except output enable (G) and linear burst order (LBO) are clock (CK) controlled through positive- edge-triggered noninverting registers. Write cycles are internally self-timed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, a flow-through SRAM allows output data to simply flow freely from the memory array. * 3.3 V LVTTL and LVCMOS Compatible * MCM63Z737/MCM63Z819-11 = 11 ns Access/15 ns Cycle (66 MHz) MCM63Z737/MCM63Z819-15 = 15 ns Access/20 ns Cycle (50 MHz) * Selectable Burst Sequencing Order (Linear/Interleaved) * Internally Self-Timed Write Cycle * Single-Cycle Deselect * Byte Write Control * ADV Controlled Burst * 100-Pin TQFP Package
MCM63Z737 MCM63Z819
TQ PACKAGE TQFP CASE 983A-01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
2/6/98
(c) Motorola, Inc. 1998 MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819 1
PIN ASSIGNMENT
SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS CK SW CKE G ADV NC NC SA SA DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VSS VDD VSS DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa
TOP VIEW MCM63Z737
MCM63Z737DMCM63Z819 2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS CK SW CKE G ADV NC NC SA SA NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS VSS VDD VSS DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
TOP VIEW MCM63Z819
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819 3
MCM63Z737 PIN DESCRIPTIONS
Pin Locations 85 89 87 (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 86 31 Symbol ADV CK CKE DQx Type Input Input Input I/O Description Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. Clock: This signal registers the address, data in, and all control signals except G and LBO. Clock Enable: Disables the CK input when CKE is high. Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d).
G LBO
Input Input
Asynchronous Output Enable. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low - linear burst counter. High - interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Burst Address Inputs: The two LSB's of the address field. These pins must preset the burst address counter values. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: Enables write to byte "x" (byte a, b, c, d) in conjunction with SW. Has no effect on read cycles. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 36, 37
SA SA0, SA1
Input Input
93, 94, 95, 96 (a) (b) (c) (d) 98 97 92 88 15, 16, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 64, 66, 67, 71, 76, 90 38, 39, 42, 43, 83, 84
SBx SE1 SE2 SE3 SW VDD VDDQ VSS NC
Input Input Input Input Input Supply Supply Supply --
MCM63Z737DMCM63Z819 4
MOTOROLA FAST SRAM
MCM63Z819 PIN DESCRIPTIONS
Pin Locations 85 89 87 (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 86 31 Symbol ADV CK CKE DQx G LBO Type Input Input Input I/O Input Input Description Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. Clock: This signal registers the address, data in, and all control signals except G and LBO. Clock Enable: Disables the CK input when CKE is high. Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). Asynchronous Output Enable. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low - linear burst counter. High - interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Burst Address Inputs: The two LSB's of the address field. These pins must preset the burst address counter values. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: Enables write to byte "x" (byte a, b) in conjunction with SW. Has no effect on read cycles. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 36, 37
SA SA0, SA1
Input Input
93, 94 (a) (b) 98 97 92 88 15, 16, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 64, 66, 67, 71, 76, 90 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 83, 84, 95, 96
SBx SE1 SE2 SE3 SW VDD VDDQ VSS NC
Input Input Input Input Input Supply Supply Supply --
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819 5
TRUTH TABLE
CK L-H L-H L-H L-H L-H CKE 1 0 0 0 0 E X False True True X SW X X 0 1 X SBx X X V X V (W) X (R, D) ADV X 0 0 0 1 SA0 - SAx X X V V X Hold Deselect Load Address, New Write Load Address, New Read Burst Continue Next Operation Input Command Code H D W R B Notes 1, 2 1, 2 1, 2, 3, 4, 5 1, 2 1, 2, 4, 6, 67
NOTES: 1. X = don`t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics. 2. E = true if SE1 and SE3 = 0, and SE2 = 1. 3. Byte write enables, SBx, are evaluated only as new write addresses are loaded. 4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high. 5. A write with SBx not valid does load addresses. 6. A burst write with SBx not valid does increment address. 7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deselect cycle.
WRITE TRUTH TABLE
Cycle Type Read Write Byte a Write Byte b Write Byte c (See Note 1) Write Byte d (See Note 1) Write All Bytes NOTE: 1. Valid only for MCM63Z737. SW H L L L L L SBa X L H H H L SBb X H L H H L SBc (See Note 1) X H H L H L SBd (See Note 1) X H H H L L
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
MCM63Z737DMCM63Z819 6
MOTOROLA FAST SRAM
INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM
INPUT COMMAND CODE CK D DESELECT B W NEW WRITE B R NEW READ B H HOLD
CONTINUE DESELECT
BURST WRITE
BURST READ
CKE
E
FALSE
TRUE
TRUE
SA0 - SAx
VALID
VALID
ADV
SW
SBX
VALID
VALID
NOTE: Cycles are named for their control inputs, not for data I/O state.
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819 7
B B D R BURST READ W R B NEW WRITE W D BURST WRITE W
D
B D R NEW READ W
R
B R DESELECT W
KEY: CURRENT STATE (n) TRANSITION NEXT STATE (n + 1)
D
INPUT COMMAND CODE
NOTES: 1. Input command codes (D, W, R, and B) represent control pin inputs as indicated in the Truth Table. 2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks any state change.
Figure 1. ZBT RAM State Diagram
STATE CK
n
n+1
n+2
n+3
COMMAND CODE
DQ CURRENT STATE NEXT STATE
Figure 2. State Definitions for ZBT RAM State Diagram
MCM63Z737DMCM63Z819 8
MOTOROLA FAST SRAM
D B HIGH-Z R W
R B DATA OUT (Q VALID)
D D W R HIGH-Z (DATA IN)
W B
KEY: CURRENT STATE (n) INPUT COMMAND CODE NEXT STATE n+1 NOTES: 1. Input command codes (D, W, R, and B) represent control pin inputs as indicated in the Truth Table. 2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks any state change.
Figure 3. Data I/O State Diagram
STATE CK
n
n+1
n+2
n+3
COMMAND CODE
DQ CURRENT STATE NEXT STATE
Figure 4. State Definitions for ZBT RAM State Diagram
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819 9
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Input Voltage (Three State I/O) Output Current (per I/O) Package Power Dissipation Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin, Vout VIT Iout PD Tbias Tstg Value - 0.5 to + 4.6 VSS - 0.5 to VDD - 0.5 to VDD + 0.5 VSS - 0.5 to VDDQ + 0.5 20 1.3 - 10 to 85 - 55 to 125 Unit V V V V mA W C C 3 2 2 2 Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady-state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single-Layer Board Four-Layer Board Symbol RJA RJB RJC Max 40 25 17 9 Unit C/W C/W C/W Notes 1, 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM63Z737DMCM63Z819 10
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 5%, TA = 0 to 70C Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage I/O Supply Voltage Ambient Temperature Input Low Voltage Input High Voltage Input High Voltage I/O Pins Symbol VDD VDDQ* TA VIL VIH VIH2 Min 3.135 3.135 0 - 0.3 2 2 Typ 3.3 3.3 -- -- -- -- Max 3.465 VDD 70 0.8 VDD + 0.3 VDDQ + 0.3 Unit V V C V V V
* VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels. VIH
VSS
VSS - 1.0 V
20% tKHKH (MIN)
Figure 5. Undershoot Voltage DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDDQ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes Supply Current for Both VDD and VDDQ Hold Supply Current (Device Selected, Freq = Max, VDD = Max, VDDQ = Max, CKE VDD - 0.2 V, All Inputs Static at CMOS Levels) CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels) TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels) Output Low Voltage (IOL = 8 mA) Output High Voltage (IOH = - 8 mA) Symbol Ilkg(I) Ilkg(O) IDDA IDD1 Min -- -- -- -- Typ -- -- -- -- Max 1 1 300 15 Unit A A mA mA 2, 3, 4 6 Notes 1
ISB2 ISB3 VOL VOH
-- -- -- 2.4
-- -- -- --
5 25 0.4 --
mA mA V V
5, 6 5, 7
NOTES: 1. LBO has an internal pullup and will exhibit leakage currents of 5 A. 2. Reference AC Operating Conditions and Characteristics for Input and Timing. 3. All addresses transition simultaneously low (LSB) then high (MSB). 4. Data states are all zero. 5. Device in deselected mode as defined by the Truth Table. 6. CMOS levels for I/O's are VIT VSS + 0.2 V or VDDQ - 0.2 V. CMOS levels for other inputs are Vin VSS + 0.2 V or VDD - 0.2 V. 7. TTL levels for I/O's are VIT VIL or VIH2. TTL levels for other inputs are Vin VIL or VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min -- -- Typ 4 7 Max 5 8 Unit pF pF
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819 11
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 5%, TA = 0 to 70C Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 6 Unless Otherwise Noted RJA Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63Z737-11 MCM63Z819-11 66 MHz Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Output Enable to Output Valid Clock High to Output Active Output Hold Time Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Setup Times: Address ADV Data In Write Chip Enable Clock Enable Address ADV Data In Write Chip Enable Clock Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX tGLQX tGHQZ tKHQZ tADKH tLVKH tDVKH tWVKH tEVKH tCVKH tKHAX tKHLX tKHDX tKHWX tKHEX tKHCX Min 15 6 6 -- -- 1.5 1.5 0 -- 1.5 2.5 2.5 2 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 Max -- -- -- 11 6 -- -- -- 4.5 4.5 -- MCM63Z737-15 MCM63Z819-15 50 MHz Min 20 8 8 -- -- 1.5 1.5 0 -- 1.5 2.5 2.5 2 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 Max -- -- -- 15 7 -- -- -- 5 5 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 4, 5 4 4, 5 4, 5 4, 5 3 3 Notes N
Hold Times:
--
--
ns
NOTES: 1. Write is defined as any SBx and SW low. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADV is low. 2. All read and write cycle timings are referenced from CK or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at 200 mV from steady state.
OUTPUT Z0 = 50 RL = 50 1.5 V
Figure 6. AC Test Load
MCM63Z737DMCM63Z819 12
MOTOROLA FAST SRAM
tKHKH tKHKL CK tAVKH
tKLKH
tKHAX SA0 - SAx tWVKH SW tWVKH SBx tEVKH tKHEX E tLVKH ADV tCVKH CKE
tKHWX
tKHWX
tKHLX
tKHCX
G tGLQX tGLQV DQ tDVKH tKHDX DQ tKHQV tKHQX1 DQ Q D tKHQX tKHQZ Q Q
tGHQZ
Figure 7. AC Timing Parameter Definitions
MOTOROLA FAST SRAM
MCM63Z737DMCM63Z819 13
MCM63Z737DMCM63Z819 14
READ/WRITE CYCLES WITH HOLD AND DESELECT CYCLES
B C D E F G H I J W D H R W R H W R D W R D Q(A0) D(B0) Q(C0) D(D0) Q(E0) D(F0) Q(G0) D(H0) Q(I0)
CK
ADDRESS
A
COMMAND CODE
R
DQ
NOTE: Command code definitions are shown in Truth Table.
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
READ CYCLES (SINGLE, BURST, AND BURST WRAP-AROUND)
CK A B C R R R B B B B B B B DQ Q(A0) Q(B0) Q(B1) Q(B2) Q(B3) Q(C0) Q(C1) Q(C2) Q(C3) Q(C0)
ADDRESS
COMMAND CODE
NOTE: Command code definitions are shown in Truth Table.
MCM63Z737DMCM63Z819 15
MCM63Z737DMCM63Z819 16
WRITE CYCLES (SINGLE, BURST, AND BURST WRAP-AROUND)
CK A B C W W W B B B B B B B DQ D(B0) D(B1) D(B2) D(A0) D(B3) D(C0) D(C1) D(C2) D(C3) D(C0)
ADDRESS
COMMAND CODE
NOTE: Command code definitions are shown in Truth Table.
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
READ, WRITE, READ COHERENCY WITH HOLD, AND DESELECT CYCLES
A B B C C D D E R R W R W B B D W H R R Q(A0) D(C1) D(B0) Q(B0) D(C0) Q(C0) Q(C1) D(D0) Q(D0) Q(E0)
CK
ADDRESS
COMMAND CODE
DQ
NOTE: Command code definitions are shown in Truth Table.
MCM63Z737DMCM63Z819 17
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
63Z737 63Z819
XX
X
X
Blank = Trays, R = Tape and Reel Speed (11 = 11 ns, 15 = 15 ns) Package (TQ = TQFP)
Full Part Numbers -- MCM63Z737TQ11 MCM63Z737TQ11R MCM63Z819TQ11 MCM63Z819TQ11R
MCM63Z737TQ15 MCM63Z737TQ15R MCM63Z819TQ15 MCM63Z819TQ15R
MCM63Z737DMCM63Z819 18
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQ PACKAGE 100-PIN TQFP CASE 983A-01
4X
e 0.20 (0.008) H A-B D
2X 30 TIPS
0.20 (0.008) C A-B D -D-
80 81 51 50
e/2
B E/2 B VIEW Y E1 E E1/2
BASE METAL PLATING
-X- X=A, B, OR D
-A-
-B-
b1 c
100 1 30
31
D1/2 D1 D
2X 20 TIPS
D/2
0.13 (0.005)
0.20 (0.008) C A-B D
A -H- -C-
SEATING PLANE
q
2
0.10 (0.004) C
q
3 VIEW AB
0.05 (0.002)
S
S
q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0 7 0 --- 11 13 11 13 INCHES MIN MAX --- 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 --- 0.003 --- 0.003 0.008 0 7 0 --- 11 13 11 13
1 0.25 (0.010)
GAGE PLANE DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2
q
A2
R2
A1
R1
L2 L L1 VIEW AB
q
1 2 q3
q q
MOTOROLA FAST SRAM
EEEE CCCC EEEE CCCC
b
M
c1
C A-B
S
D
S
SECTION B-B
_ _ _ _
_ _ _
_ _ _ _
_ _ _
MCM63Z737DMCM63Z819 19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
MfaxTM : RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274
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MCM63Z737/D MOTOROLA FAST SRAM

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